1. Field of the Invention
This invention pertains generally to digital logic circuitry, and more particularly to reducing power consumption using event driven logic wherein the clock signal is only propagated within the circuit after a true logic operation is performed.
2. Description of the Background Art
Conventional logic circuitry often utilizes a clock signal which is received by various levels of gating within the circuitry for synchronizing the state changes within the circuitry so as to eliminate race conditions and other similar problems. As a result, the clock signal is applied to a number of gates within each logic block or section. A predetermined gate capacitance exists for each gate which is subject to repeated charge and discharge cycles following clock activity. Consequently, circuit power consumption is increased by repetitive charging and discharging, even when no net circuit activity results. Furthermore, clock signal loading can be substantially increased which requires higher power clock sources and additional dissipation.
For example, FIG. 1 depicts a conventional four-input AND gate 10 implemented in CMOS static logic having data inputs 12 and a data output 14. All four inputs 12 (IN1–IN4) must be retained “high” to allow the voltage at node A to discharge to VSS (logic state=“low”) through transistors 16a, 18a, 20a, 22a, while transistors 16b, 18b, 20b, 22b, are retained in an off state. With node A driven low at the input of inverter 24, signal output OUT 14 transitions to VDD (logic state=“high”). It should be noted that CMOS static logic is considered extremely stable and is in widespread use within conventional circuit designs, particularly within integrated circuits. One drawback of this static topology is that each input signal is gated to both PMOS and NMOS transistors, thereby subjecting the inputs to large gate load capacitances and their associated charge delays.
To improve the speed of CMOS static logic, various kinds of dynamic logic have been proposed. The purpose of these proposed designs is to minimize gate loading and to control circuit operation in response to a clock signal. Dynamic logic circuits also provide a ready means of synchronizing signal state changes between various logic stages within a digital logic section or device.
FIG. 2 depicts a conventional four-input AND gate 30 implemented with dynamic logic which is generally referred to as “domino” logic. Inputs 32 (IN1–IN4) are connected to transistors 36, 38, 40, 42 respectively. A clock signal CLK 44 is connected to complementary transistors 46, 48. The output inverter 50, with a keeper circuit 52, drives output signal OUT 34. In response to CLK going low, node A and output signal OUT 34 are precharged at VDD (high) and VSS (low) levels, respectively. It will be noted that since transistor 48 is held inactive during precharging, the state of the inputs does not affect precharging of node A.
The precharging is performed during a clock phase referred to as a “precharge phase” which occurs in the depicted circuit while the clock is held in a low state. It should be appreciated, however, that the precharge clock phase may be of either polarity and subject to other conditions, depending upon circuit implementation.
Circuit element 52 is implemented as a “keeper” circuit to maintain the voltage of node A. The “keeper” shown is preferably implemented using a small transistor 52 that exhibits a higher on-state resistance than the other transistors driving node A, thereby allowing its state to be over-ridden.
Upon clock signal CLK 44 transitioning to a high state, an evaluation phase is entered within which the state of the inputs is readily reflected in data output 34. Consider the case of satisfying the AND logic configuration with all inputs 32 being held high as the evaluation phase is entered. Node A is discharged to low through transistors 36–42, 48 whereupon output signal OUT 34 switches to high. If any inputs 32 are held low as the evaluation phase commences, then node A is retained high and output signal OUT 34 remains low.
Each input is gated to a single NMOS transistor, wherein the resultant gate load capacitance is smaller than that provided by conventional CMOS static logic as depicted in FIG. 1. As the mobility of electrons is typically faster than that of holes by more than a factor of two, the size of NMOS transistors is also typically less than half the size of their PMOS transistor counterparts. Therefore, the effective gate load capacitance of dynamic logic can be approximately one-third of that exhibited by static logic. As a consequence of reducing gate load capacitance, dynamic logic can operate at significantly higher clock rates than similar CMOS static logic. A typical dynamic circuit can operate approximately thirty percent (30%) faster than a substantially equivalent static circuit. However, dynamic logic circuits are subject to high power consumption levels.
Considering the operation of dynamic circuit 30 of FIG. 2, it will be noted that at the falling edge of clock signal CLK 44, the gate of transistor 46 is discharged by clock signal CLK 44, thereby activating transistor 46 to precharge node A. Similarly, the gate of transistor 48 is discharged to deactivate transistor 48, wherein charge current is driven to node A regardless of the state of output OUT 34. Consider the case where inputs IN1, IN2 and IN3 are being held high while input IN4 is held low during the evaluation phase (i.e. CLK is high). As a result of transistor 42 remaining in an off state, a non-satisfied AND condition exists, wherein the voltage of node A is not discharged and remains at the precharge level VDD (high). However, upon clock signal CLK 44 transitioning low, transistor 46 is switched-on to charge node A toward VDD while the gate capacitance of transistor 48 is discharged. This circuit illustrates that even without circuit activity, the capacitance associated with transistors 46 and 48 are being charged or discharged when clock input CLK 44 transitions either low or high.
It should therefore be appreciated that in conventional dynamic logic circuitry, as described, the clock signal (CLK) repeatedly charges and discharges a number of gate capacitances whether or not the state of the logic circuit is subject to change. As a result, power is always consumed within a dynamic logic stage subject to receipt of an active clock. It should be appreciated that with regard to the four input AND gate shown in FIG. 2, the probability of circuit activity that may result in a change of the output signal is one out of sixteen (assuming equal input probabilities). As a result, power is consumed unnecessarily by the clock without any circuit operation for fifteen out of the sixteen possible input combinations. It should be appreciated that this “inactive” mode power consumption may be larger or smaller than in the four input AND gate example and is dependent upon the circuit configuration (i.e. number of inputs, gating, use of additional combinatorial circuits and sequential circuits, and so forth) and signal activity within the given application.
FIG. 3 exemplifies a sequential logic circuit 70 to illustrate that clock signal related power losses are also common problems within sequential logic circuits. A conventional flop-flop device 70 (D-FF) is depicted in the figure having a data input D 72 and a clock signal input CLK 74, while complementary outputs Q 76 and Q-bar 78 are provided.
During flip-flop operation, as clock signal CLK 74 goes low, node X is precharged to VDD (high) through transistor 80. An inverted clock signal is also generated from clock signal CLK 74 propagating through an odd number of inverters 82, 84, 86. An OR'ed grouping of transistors 80, 88 and 90 can provide for charging of node X, while an AND'ed series of transistors 92, 94 and 96 can operate to control the discharging of node X. A latching section is shown comprising four transistors 98, 100, 102, 104 that operate in response to clock signal CLK 74 and the state of charge of node X to drive an output stage having inverters 106, 108.
After clock signal CLK 74 transitions to low, the inverted clock signal CLKD-bar transitions to high following the inverter propagation delay, whereupon transistor 96 and transistor 104 switch to an on state. Output data is driven by transistor 98 in conjunction with inverter 106 and 108 preferably implemented as a “keeper”.
First, the situation is considered in which the latched data at node Q 76 is low, as set by a previous cycle, while the input signal D is held high. In response, transistor 94 is retained in an on state, whereupon as clock signal CLK 74 transitions high entering the evaluation phase, transistor 92 and transistor 100 are switched-on and node X is discharged toward VSS (low) through transistors 92, 94 and 96 until transistor 96 is switched-off following the propagation delays associated with inverters 82, 84, 86. As node X is discharged, transistor 98 is switched-on and node Q 76 and Q-bar 78 transition to high and low, respectively. When the latched data output is being held high as data input D 72 is retained low, node X remains at the precharged high level (VDD) because transistor 88 is switched-on and transistor 94 is switched-off. When clock signal CLK 74 transitions to a high, then node Q 76 is discharged to VSS (low) through transistors 100, 102, 104 until CLKD-bar transitions to low following the inverter propagation delays. Consequently, the latched data at node Q 76 is switched high to low and Q-bar transitions to high.
This D flip-flop circuit would be operable at sufficiently high frequencies to allow implementation of high frequency pipeline architectures. Unfortunately, the substantial power losses which arise within the dynamic logic circuits as a consequence of repetitive charging and discharging make the circuit generally less desirable for these applications.
It will be appreciated that in the case where clock signal CLK 74 transitions to high (evaluation phase), when the latched data is high and data input D is also high, then node X is discharged to VSS (low) and node Q is connected to VDD (high) through transistor 98. However, as the latched data is already high, no net circuit activity is occurring as a result of the operation of transistor 98, and yet the clock signal CLK 74 must still charge the gate capacitances of transistors 92, 100. In addition, when clock signal CLK 74 transitions to low, the gate capacitances of transistor 92 and transistor 100 are discharged and the delay pulse circuit is activated to charge the gate capacitance of transistors 96, 104. These operations are repeated even though the output data remains unchanged (high) while the clock signal CLK 74 is running. As a result, a substantial percentage of the operating power is unnecessarily consumed by the unproductive activity of clock signal CLK 74, which is subject to loading even when no desired circuit state changes occur.
It has been shown that both combinatorial and sequential logic circuits are similarly subject to capacitive loading of the clock signal, wherein circuit power is consumed even when no net (productive) circuit activity is occurring.
Therefore, a need exists for a logic circuit that exhibits lower gate capacitance losses in response to the activity of a dynamic clock signal, wherein overall circuit operating power may be reduced. The present invention satisfies those needs, as well as others, and overcomes the deficiencies of previously developed dynamic clocking methods and circuits.